Recently, in memory devices of large capacity, replacement of defective memory cells by redundancy circuits is executed for eliminating errors caused by defects of memory cells. A redundancy circuit of this kind is composed of spare memory cells for substituting for defective memory cells if any, and a circuit for storing addresses of the defective memory cells (hereinafter referred to as defect address) and conducting the switching from the defective memory cells to the spare memory cells. Methods roughly classified into the following two kinds are applicable as a method of storing defect addresses, depending on a type of the device used.
First of all, for volatile memories such as DRAM and SRAM, a plurality of fuses formed with polysilicon, metal, etc. are provided in a device, and the storage of defect addresses is carried out by electrically breaking the fuses, or breaking the same by a laser beam or the like.
Conventionally, since memory cells are nonvolatile per se in EPROMS, flash memories, and the like, the memory cells are, instead of fuses, adopted as memory elements so as to store defect addresses to be redundancy-saved and initial states of the device.
FIG. 5 is a circuit diagram showing a memory circuit for storing defect addresses to be redundancy-saved, or a memory circuit for storing initial states of the device, used in a conventional EPROM or flash memory. Such a memory circuit is hereinafter referred to as an option circuit. Such an option circuit is disclosed by the U.S. Pat. No. 5,267,213 (Issue Date: Nov. 30, 1993), for example.
An option circuit 1a is designed so as to store one bit of, for example, a defect address, composed of two floating-gate-type transistors (hereinafter referred to as floating gate transistors) 2 and 3, N-type transistors 4, 5, 6, and 7, and P-type transistors 8 and 9. Generally, such a memory circuit is called as CAM (content addressable memory) cell. A bias voltage V gate that is an output of a bias voltage generating circuit 10 is supplied to each gate of the floating gate transistors 2 and 3 in the option circuit 1a thus designed. To each gate of the N-type transistors 4 and 5, an output of a bias voltage generating circuit 11 is commonly supplied.
These P-type transistor 8, N-type transistor 4, and floating gate transistor 2 are connected in series in this order between a power source voltage Vcc level and a power source voltage Vss level (ground level), while likewise these P-type transistor 9, N-type transistor 5, and floating gate transistor 3 are connected in series in this order between the power source voltage Vcc level and the power source voltage Vss level.
A gate of the P-type transistor 8 is connected with a node N4 that connects the P-type transistor 9 and the N-type transistor 5 with each other, while a gate of the P-type transistor 9 is connected with a node N3 that connects the P-type transistor 8 and the N-type transistor 4 with each other. Further, a program voltage VPRG (about 10-12V) is supplied to each drain of the N-type transistors 6 and 7, while program signals PRG1 and PRG2 are supplied to gates of the N-type transistors 6 and 7, respectively.
A source of the N-type transistor 6 is connected with a node N1 that connects the floating gate transistor 2 and the N-type transistor 4 with each other, while a source of the N-type transistor 7 is connected with a node N2 that connects the floating gate transistor 3 and the N-type transistor 5 with each other.
The option circuit 1a outputs an output OUT 1 via the node N4 that connects the P-type transistor 9 and the N-type transistor 5 with each other. A plurality of such option circuits are provided (for conveniences' sake, FIG. 5 shows a case where two of the same are provided), and an option circuit 1b is designed so that program signals PRG3 and PRG4 are supplied to gates of the N-type transistors 6 and 7, respectively, and that an output OUT 2 is outputted via the node N4 that connects the P-type transistor 9 and the N-type transistor 5 with each other.
The following description will explain an operation in accordance with the foregoing arrangement. First of all, a case where this option circuit 1a is made to store a single bit will be explained below. Specifically, a case where a "0" state of binary logic is stored (programmed) by the option circuit 1a will be explained as an example of the operation.
All memory cells of the floating gate type (transistors 2 and 3 ) inside the foregoing option circuit 1a are in a state of being erased by ultra violet (ultra-violet erasure), and their threshold voltages are neutralized to about 2V to 3V.
The bias voltage generation circuit 10 is normally designed to output the power source voltage Vcc, but an output of the bias voltage generating circuit 10 is set to as high as not lower than 10V, whereas a bias voltage outputted by the bias voltage generating circuit 11 is lowered to a Vss level, upon programming. This causes the N-type transistors 4 and 5 to be turned off, while only the program signal PRG1 is raised to about 7V to 8V.
In this state, for a predetermined period of time, the program voltage VPRG (about 10V to 12V) is supplied to the drains of the N-type transistors 6 and 7, but since the N-type transistor 7 is off while the N-type transistor 6 is on, a voltage of about 6V to 7V is applied to the drain side (the foregoing node N1) of the floating gate transistor 2 via the N-type transistor 6.
This provides current flow between the drain and source of the floating gate transistor 2. Hot electrons generated by the current are injected into a floating gate of the floating gate transistor 2 by a bias voltage (Vgate) applied to the floating gate transistor 2. This causes the threshold voltage of the transistor 2 to increase. As a result, the threshold voltage is raised to about the power source voltage Vcc or above. On the other hand, the threshold voltage of the floating gate transistor 3 remains neutralized to about 2V to 3V. Thus, with a difference between the threshold voltages of the floating gate transistors 2 and 3, the option circuit 1 is made to store "0". This is identical to write-in to a common hot-electron-injected EPROM, flash memory, etc.
Next, a case where "1" is stored by the option circuit 1a will be explained below.
Only the program signal PRG2 is set not lower than the power source voltage Vcc. In this state, for a predetermined period of time, the program voltage VPRG (about 10V to 12V) is supplied to the drains of the N-type transistors 6 and 7. Since the N-type transistor 6 is off while only the N-type transistor 7 is on, a voltage of about 6V to 7V is applied to the drain side (the foregoing node N2) of the floating gate transistor 3 via the N-type transistor 7. This provides current flow between the drain and source of the floating gate transistor 3.
The threshold voltage of the transistor 3 is raised as is in the aforementioned case. On the other hand, the threshold voltage of the floating gate transistor 2 remains neutralized to about 2V to 3V. Thus, with a difference between the threshold voltages of the floating gate transistors 2 and 3, the option circuit 1a is made to store "1".
All the option circuits 1a in the CAM are subjected to the foregoing process before shipment of the device, so that either "0" or "1" is stored (programmed) in each.
Next, an operation in the case where the device is used by a user after shipment of the device thus programmed will be described below. For conveniences' sake, "0" is assumed to be stored (programmed) in the option circuit 1a. When the device is powered on, the bias voltage Vgate as an output of the bias voltage generating circuit 10 is set to Vcc, and an output VB of the bias voltage generating circuit 11 is boosted to about twice of the threshold voltages of the N-type transistors 4 and 5 (boosted to about 2V). As a result both the N-type transistors 4 and 5 become conductive. Here, gates of the transistors 2 and 3 are supplied with the bias voltage Vgate (=power source voltage Vcc), and this bias voltage Vgate is a medial voltage that is higher than the threshold of the floating gate transistors 3, while lower than the threshold voltage of the floating gate transistor 2. Therefore, the floating gate transistor 3 is turned on, while the floating gate transistor 2 is turned off.
Accordingly, the output OUT1 (output of the option circuit 1a) is pulled down to the "L" level by the floating gate transistor 3 and the N-type transistor 5. Further, since the output OUT1 is supplied to the gate of the P-type transistor 8, the fall of the output OUT1 to the "L" level causes the P-type transistor 8 to become conductive, but since the floating gate transistor 2 is non-conductive, the potential at the node N3 is pulled up completely to the level of the power source voltage Vcc. This pulling-up of the potential at the node N3 to the Vcc level causes the P-type transistor 9, whose gate is supplied with the same, becomes non-conductive, while the node N4 becomes completely to the Vss level. At this stage, the nodes N3 and N4 are completely at the power source voltage Vcc level and at the power source voltage Vss level, respectively, and therefore, DC current no longer flows. The output OUT1 becomes "0".
Incidentally, the case where the output OUT1 becomes "1" is a case in which the relationship between the floating gate transistors 2 and 3 regarding the height of threshold voltages thereof is inverted, and the subsequent process is identical to the operation described above. Therefore, detailed description is omitted herein.
The option circuit 1a operates in the manner as described above, and after being powered on, the foregoing state is latched. An identical state is latched for each of the all other option circuits 1b, 1c (not shown), . . . , and either "0" or "1" is outputted from each circuit.
The above-described conventional option circuit 1a shown in FIG. 5, however, undergoes a drawback as described below.
When the power source voltage Vcc becomes lower, this causes the voltage supplied to gates of flash cells (floating gate transistors 2 and 3 ) to become lower as well. The threshold voltages of the flash cells (about 2V to 3V) are extremely high as compared with threshold voltages of other transistors (about 1V), and when the gate voltages become lower than the threshold voltages of the flash cells, the option circuit cannot operate.
This may be, for example, solved by adding a voltage obtained by raising the power source voltage Vcc to the bias voltage Vgate. Alternatively, this may be solved by erasing the flash cells and lowering the threshold voltages. Such schemes, however, are disadvantageous since time required for testing may be increased and reliability may be adversely affected.
In the case of only actuation with a low voltage, a fixed voltage obtained by raising the power source voltage Vcc may be added to the bias voltage Vgate. However, in the case where both actuation with a low voltage and actuation with a normal voltage are required, such simple addition of the boosted power source voltage Vcc results in that, when the power source voltage Vcc is a normal voltage, the bias voltage Vgate becomes too higher for the boost. When the bias voltage Vgate is thus too high, the floating gate transistors 2 and 3 are likely not turned off, thereby not allowing the option circuit 1a shown in FIG. 5 to output "1" as the output OUT1.
To overcome this problem, additional provision of a voltage detecting circuit is required for switching the gate voltage between the normal voltage and the low voltage. In this case, however, behaviors upon switching of the voltage mode, variation of the switching voltage depending on changes in the process and the operational environments, and power consumption by the detecting circuit will arise as problems. Correspondence to the normal voltage or the low voltage may be set by option, but a circuit for setting the option itself cannot normally operate if the supplied voltage varies. Therefore, this cannot be an overall solution.